Working on the board layout for @Ash 's circuit. I will likely mess with it on a small prototype board before ordering in an actual board. The circuit as of this moment in time will only be used in two flashers so I don't think I can justify the cost of ordering in custom boards... however If I start replacing controller boards in other lights. perhaps it might be worth while to evolve from proto-boards to real... who knows what the future holds.

this mock up is not done yet. I am sure I made a mistake somewhere I will find later. I am not well rested lol.

I see you have very small clearances at a few places, which will likely lead to short circuits.
Learn to set up and really use DRC (Design Rule Check) function of the CAD software you are using on your designs and rigorously clear all real violations.
With the rules don't push the manufacturing (that includes your ability to solder things without shorts) to the limits by e.g. allowing smalled clearances or distances, it will bite you into your rear later...

Build it on a plug-in solderless breadboard and get a sense of it before you even start soldering

That is my first step with many circuits, including ones where i am really pushing the breadboard limits (switching power supply on a breadboard is significantly affected by stray capacitance, but still useful to weed out all sorts of overlooks and errors, and get sense of component values beyond the initial estimation/calculation)



The capacitors are mostly <1uF ceramic (use Kemet Goldmax series). They are small and flat (you can fit them side by side at 0.1" spacing, at least as long as you dont put 1uF or more in there), except the 10uF one which is a little cube (would fit in 0.2" space)

Some ceramic capacitors have 0.1" and some 0.2" lead spacing. See what's available where you get them

The 10uF is the only one which you are likely to switch to an electrolytic, like if you want to put something of higher capacity in there, or due to cost (an electrolytic probably cost less than 10uF ceramic), though it may have a little higher leakage. Placing 2 parallel spots for ceramic capacitors is also an option




What you have drawn is well within the capabilities of all PCB manufacturers and even low tech PCB manufacturing, but here is a consideration about leakage currents :

The high resistor values (chosen to save battery) mean that the circuit is sensitive to leakages from contamination/dampness. Specifically the networks connected to high impedances : Pins 2, 6, 5 of both 555's, link between D3 and R6, Gate of output MOSFET

Avoid making those traces large or shoving them in tight spaces if possible (where little contamination on the board surface may make a significant resistive leakage between them and something else)

For the final production, go for a board with solder mask to isolate most of the trace surface, and protect it with conformal coating if needed



DRC is a useful tool, but it does not tell the whole story

DRC (in its most basic form) just verifies that you keep the minimum set distance between traces, an other distance-based rules

Here we are talking about contamination, essentially a parasitic film resistor. Obviously, the width of the film (length of parallel traces) will affect the resistance just as much as length of the current path (distance between parallel traces). DRC does not say anything about trace length. It is up to you to design in a sensible way

Even when it is about voltages and flashover distances (typical use case of DRC), electrical breakdown is a statistical effect. If the safe distance for a certain voltage is 3.0mm (for example), a board filled with comb pattern of traces spaced at 3.0mm (pefrectly ok according to DRC), will be much less reliable and less safe than a board with reasonable design, where in one spot the distance is 2.95 (which will make the DRC flag it)

And then there are all the additional considerations : Is it about distance between 2 open solder joints ? Is it between 2 traces, both insulated by solder mask ? A solder joint and a trace ? etc



I would recommend leaving an option for assymetrical duty cycle of the fast flicker for further experimenting (add place for a diode and resistor like D3+R6 in the 2nd 555)



If you want the Kicad file just ask. (Also, i highly recommend Kicad in general both for circut drawing and PCB design, it's my main tool - Along with Qelectrotech for electrical wiring drawings)

Indeed, a clean DRC result won't guarantee just by itself a good PCB design.
But a "dirty" DRC result pretty much guarantees the PCB design is bad. So to have DRC result without any real violations is pretty much absolute minimum.

Here this is low voltage thing, I wouldn/t expect any issues with "film resistors" forming on the PCB, nor with flashovers.
But around pin 5 of the "bottom" 555 and around one of the terminals of the small transistor (? - in the top left cornet) I see the spacing really extremely small (my guess barely 0.1mm; I would not go below 0.3mm, mainly around solder joints), even for such coarse picture...

But what exactly is the purpose of this circuit?

The DRC result depends on how you set the DRC rules. And here things may get interesting

There are some hard limits on spacing :
 - Minimum spacing required for insulation class : Basic, reinforced, etc
 - Board manufacturing : The board house is technically unable to make a board with smaller spacing than this

And some not so hard limits :
 - Spacing for functional insulation, where it's up to you to decide
 - The board house, the soldering process (especially wave), or you, may prefer to have bigger distances than the abs min nominals

Consider a big complex circuit. You may want to have some design margin in most of it (have clearance that is more than just the bare minimum to hold the voltage, have distances that don't challenge the board house), and may have one complicated spot where you may have to bend the rules a little (within reason) to resolve some other design constraint

And here you have options : Either set the DRC to the "higher standard" and handle manually an exception when it flags a violation in the complicated place, or set the DRC (for the entire board) to a "bare minimum standard" so that the one complicated place won't set off the alarm

Pretty much everything that can happen in "light" DRC violations is a statistical phenomena (the odds of electrical breakdown under additional external factors, the odds of a solder droplet forming between too close pads after wave soldering, etc)

It is better to keep as much of the board as possible to a "higher standard", and handle manually the complicated spot (e.g. by more careful inspection in that spot, adding a drop of lacquer insulation externally, accepting the fact that this is a weak spot as is, etc)

In particular, board houses i have worked with (in Europe and USA) specifically say in their design guidelines : If you have to make something in the board that is at our manufacturing limits, do what you have to do, but please don't make all the rest of the board the same unnecessarily

Even though you could just set the DRC to the abs min requirements and get it "clean" (and within the nominal capabilities of the board house)....

But then, your board may have lots of unnecessary weak spots, which statistically accumulate to making your device less reliable (to manufacture or to use), instead of just one which you couldn't avoid but at least have given some specific attention to



In this circuit (4.1VDC) of course we don't think about insulation breakdown

But doesn't a circuit which have 470Kohm resistors and may be used in an outdoors environment (in a unit which is never perfectly sealed), have chance to develop some leakage sufficient to throw off the timing a bit ?



In this circuit, i think it would make sense to set the CAD software to place the interconnecting wires on a grid (in this case 0.05"). This would prevent those unnecessary bad spots in the 1st place, before we even run DRC