My webcam mic is generating infinite frequency spikes when it records sound over 8khz, wich is the range of it's sheety builtin ADC, and when I record with in audacity it generates that spikes.

Here's the spectrum:


I think that my mic is doing something like this:


Here's a 44100Hz WAV recording of what it does. Turn down your volume!!!!

It sounds like the front end is deffective and so starts to oscillate on its own, oscillation probably triggered when excited to saturation. Very unlikely it has been designed this way, most likely it is really a manufacturing defect.
So a case of a warranty claim...

Thats not a factory defect, that's the way how it was designed but if it was a factory defect im not gonna replace my whole laptop for a thing that barely use. It really always happens when I record whith audacity with sample frequencies over 16000Hz, but it doesn't happen with the windows camera aplication, the high frequency sound just get filtered out.

Thats not a factory defect, that's the way how it was designed but if it was a factory defect im not gonna replace my whole laptop for a thing that barely use. It really always happens when I record whith audacity with sample frequencies over 16000Hz, but it doesn't happen with the windows camera aplication, the high frequency sound just get filtered out.

The fact it gets filtered out with the camera SW does not mean there is not a problem.
The behavior you describe is typical when a high order SD (the core of the audio ADC) internally saturates.
Normally this is supposed to be detected by the first decimation filter stage and trigger a reset of all the analog integrator stages (all integrated within the ADC IC) and by that prevets all oscillations. As a result, when the input gets overloaded, it just continues to give clamped output stream, whaich is, what one would expect from an ideal ADC.
Without this detection/reset the dynamic response of the integrator stages dramatically changes when some saturate, often yielding unstable operation. This instability then creates nearly full range amplitude ultrasonic tones which are filtered out by the digital decimatin filter if they are above the programmed bandwidth. But when they fall below the cut out, they create exactly the noise you are describing.
This detection/reset apparently does not work in your chip, very likely because it is not covered by the IC manufacture end of line test (standard SD ADC test just measures the pulse density at different DC levels, so nothing is saturated; it would require the test procedure to be tailored to the exact internal structure of the ADC, what would make it more expensive to develop plus need some additional test HW integrated within the IC - a silicon area used only once during the factory test and not doing anything in the application; so cost extra money the maker did not want to pay) and a fabrication defect just happened in that area (defects are random and it is the role of the end of line test to reject chips having the defect on them).

The design of the SD based ADC, including the initial digital processing is practically standard cookbook task, which contains the overload recovery. The main reason is, the math behind is not a trivial matter so doing it alone would be very lenghty and contain a lot of bugs b ecause of the pitfalls the concept contains. But it is very widely used concept in the industry (mainly because it allows pretty linear high resolution convertors to be made in a small silicon area using cheap digital processes), so the cookbooks, including all the overload treatment features, are widely available in the literature. So designing such ADC without such features would actually be more expensive than leaving that feature in, so I doubt anyone would make any IC without.

When it oversaturates with frequencies below 8 khz it just do normal audio clipping, but with sound over 8 khz and low saturation it does those weird things, like if the sampling frequency is matching random spots of the high frequency sound, like you see in the fractal looking graphic in the original post. Maybe that effect is in my case.

When it oversaturates with frequencies below 8 khz it just do normal audio clipping, but with sound over 8 khz and low saturation it does those weird things, like if the sampling frequency is matching random spots of the high frequency sound, like you see in the fractal looking graphic in the original post. Maybe that effect is in my case.

Well, the "fractal looking thing" is exactly, what pointed me onto the oscillation of the SD modulator. The saturation I mean is not directly visible at the decimated output, but it uses to make the output value jumping across few codes (the typical response of the digital decimation filter).
The modulator can saturate not only on absolute amplitude (input voltage too high), but as well on high dynamic change (the max voltage gets reduced at higher frequencies; exact f-V li it curve depends on the exact topology and modulator transfer function, but generally the max voltage goes down as the f increases). Usually the designs are even so the low frequency signals can not saturate the converter itself (from the analog part the upstream preamps saturate first), but usually the filters are designed so the signal gets clamped in the digital on the output. The reason is, the SD increases noise as you are approaching its ends of range, so it uses to be designed so it never operates there (a 16 bit ADC does the internal processing at least in 17 bits from -65536..65535, the output is then clamped to the -32768..32767 range of the 16 bit output).
So what may look like saturated converter means the converter itself is not saturated yet, it is just its output.
But if you put there strong HF, it may saturate the core at lower input voltages. But this saturation should be detected and the reset triggered, so it should result only into output clamping. But if this resetting does not work, i may trigger these wild oscillations (the resetting is in fact stopping it).
So I still think the ADC chip is deffective.

The chip area of this detection/reset is so tiny (we are talking about 100 gates size in the digital part and about 20 small transistor switches in the analog; compare to 100+kgates and 200 bigger transistors and 20 big capacitors in the analog for the ADC part alone; "big" and "small" is relative to the used technology, so "small" is about 0.5um^2, "big" about 100um^2), many chip makers really just play the odds of the probability of a defect being just there is very low so test only the main processing part (the parts with the "big" components) and do not test that small saturation recovery part (mainly the 20 analog transistors, as the digital uses to be covered regardless of its function just because the way how the way the test of the digital is prepared).