But clearly this UPS is controlled by the microcontroller, which also measures the output voltage. And I doubt it would use separate voltage sensing for regulation and separate for displaying the voltages in the app. Most likely it uses a common V-meter (I mean divider, ADC and processing) for both displaying the output voltage, as well as controlling the transformer tap switches.
So if it displays 250V, it means either that is what the regulation aims for (within the tolerance), or the regulation loop itself got crazy (due to input feed impedance and load behavior, a combination the thing was apparently not designed for) and it is just hunting around to reach the correct output so much, the reading after averaging (i guess the regulation uses fast ADC readouts, but the display averages/filters them out to get somewhat stable reading on the "display") it shows the voltage being higher than actually intended in average.
And essentially the same principal functionality (minus the user readout display) is in the PFC of the computer PSU. So you have a cascade of two elements which both could get crazy under some not so usual conditions, so making the combination even way more likely to go crazy...
But it could also be fault in one of them. The computer PFC very likely uses analog regulation loop, so will use analog capacitors and resistors to program the dynamic response behavior. And the main power tank capacitor is also part of this loop. So once some of them dries out and degrades, the parameters may shift so it starts become unstable by itself, or at least more sensitive for higher mains impedance (and there the boosted voltage from the UPS will have higher impedance than the direct mains when boosting, due to the extra resistance of the transformer winding, even when the UPS itself is behaving correctly). And the computer PSU oscillations may then also upset back the UPS control, throwing everything into the deep mess of unstable regulation loops.
I doubt the control problem could be in the UPS itself, as there all the dynamics is most likely implemented in the processor, so not relying on any parameter of external timing components, except of the CPU clock generation. And because this clock generation is also used for the communication and the communication to the external world is working, the CPU clock will not be defective.
The only thing that remains is some faulty switching element on some regulation step. Then the voltage would disappear completely instead of e.g. getting reduced by a few volts. But on the other way I would expect the firmware will contain some detections of such "impossible" states (the voltage dropped to zero instead of just by few V) and trip some alarm and/or safe foldback mode.
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